Ειδικά Θέματα Ελέγχου Ορθής Λειτουργίας VLSI Συστημάτων - Σχεδιασμός για Εύκολο Έλεγχο

Introduction: The need for testing,  Verification testing vs. manufacturing [parametric, logic(functional, structural)] and periodic testing, Test issues,  Problems of testing, Test economics.

Part I.TESTING

Failures, Defects and Fault Models: Terminology, Failure Classification, Failure Rate Vs Product Lifetime, Stuck-at Faults, Bridging Faults, Stuck-Open Faults, Stuck-On Faults, Delay FaultsFault Simulation: Logic simulation versus Fault simulation, Fault Simulation, Fault Coverage, Fault Dictionary, Compiled versus event driven simulators, Several implementations (Serial, Parallel, Deductive and Concurrent fault simulators) Testability Measures (SCOAP),  Test Pattern Generation: Exhaustive,  Pseudoexhaustive), (Pseudorandom (PR) and Deterministic (D-Algorithm, PODEM, FAN Fujiwara, Critical paths) tests.

Part II. DESIGN FOR TESTABILITY

(DFT) General guidelines,  test point insertion, Pseudoexhaustive testing, Scan Path Design Techniques (Types of storage devices, Types of scan, Cost of Scan, Parallel scan, Partial Scan. Built-In Self-Test (BIST): Test pattern generation, Response compression, Architectures for Test per-clock and Test per-scan BIST. Test Data Compression): Variable-to-fixed (Run-length etc), Variable-to-variable (Golomb etc), Fixed-to-variable (Huffman etc), Fixed-to-fixed (LFSR seeds). Memory testing, Digital boundary scan, IEEE Std. 1149.1), IEEE STD 1500 for testing embedded cores, SOC/IP Core Testing, Test Scheduling. Laboratory: 2x3 hours, tools learning (Design Compiler, DFT_Compiler,  and Tetramax)

Projects: 4 small projects are given to each student using benchmark circuits: a) test pattern generation for combinational circuits b) scan path insertion c) test pattern generation for circuits with scan paths and d) BIST implementation.