##start logic equivalence checker
lec -XL -nogui -color -64

##read library
read library slow_vdd1v0_basicCells.v -verilog -both

##read initial RTL design
read design labadder.vhd xxxx.vhd yyyyy.vhd -vhdl -golden

##read netlist produced from genus
read design labadder_m.v -verilog -revised

set system mode lec

add compare point -all

compare

report verification

exit